Clock signals are used for a variety of purposes in digital circuits, both on board level systems and integrated circuit (IC) devices. An integrated circuit such as a programmable logic device (PLD) typically receives one or more external reference clock signals to generate one or more internal clock signals to operate internal digital circuits. In synchronous systems, global clock signals are used to synchronize various circuits across the board or IC device. For example, internal circuits could be clocked by a first clock signal at a first clock frequency, while input/output (I/O) circuits could be clocked by a second clock signal at a second clock frequency. As the complexity of digital systems increases, clocking schemes continue to become more complicated, and there is a greater need for additional clock signals and more flexibility in generating various clock signals.
While multiple clock generating circuits could be used to generate the multiple clock signals, clock generating circuits typically consume a large amount of chip space. Therefore, most systems receive an external clock signal or use one clock generating circuit to generate a first clock signal called a reference clock signal, and derive other clock signals from the reference clock signal using specialized circuits. However, these internal clock signals must be carefully controlled to ensure proper timing in the integrated circuit. It is important for proper operation of the integrated circuit device that a generated clock signal be maintained accurately at the specified phase and frequency. This is often done by assuring that the generated clock signal is phase aligned and frequency aligned with the reference clock signal. Clock management circuits are used in integrated circuits to perform such functions as deskewing and phase shifting.
Delay-locked loops (DLLS) such as, for example, DLLs in the Virtex or Spartan Field Programmable Gate Array (FPGA) product series from Xilinx Inc. of San Jose, Calif., are one type of clock management system used to manage the propagation delay of the clock signals by using a delay line, and therefore are used for deskewing and phase shifting. As shown in FIG. 1, a deskewing circuit 102 which could comprise a delay lock loop, for example, is coupled to receive an input clock signal (clkin) and the output clock signal (clkout) from the output of the clock distribution network 106. A control circuit 106 will control the value of the delay line so that the output clock signal is in phase with the input clock signal. If the delay line in the circuit is voltage-controlled, analog circuits adjust the phase by adjusting the voltage applied to the delay line (i.e. voltage controlled delay elements). In a clocking architecture based on a tap-controlled delay (TCD) line, the number of delay elements in a delay line is selected to control the delay, where the number of the delay elements in the TCD is dictated by the lowest frequency range. However, a conventional tap-controlled delay line may be sensitive to environmental and operating conditions such as process variations, voltage, temperature, and noise. Tap-controlled delay lines can also occupy a large amount of area, and may introduce duty cycle distortion.
Delay-locked loop circuits often have a number of delay lines. A control block of a delay-locked loop circuit finds the correct amount of shifting required by all the delay lines of a portion of the circuit, commonly called the custom block, which includes the delay lines that control the phase of the clocks. Finding the delay select vectors is also known as the locking process. However, controlling delay lines in conventional devices often requires adjusting clocks in different clock domains for the locking process. Further, the control circuit of a conventional delay-locked loop must often run at a higher frequency than would otherwise be required because the delay lines are operating at the same frequency as the control block.
Conventional circuits also often require a user to set a frequency mode, such as a high frequency or low frequency mode, to lock to the reference frequency. Delay-locked loops often have low and high frequency operating modes. These operating modes, which define both input and output frequency restrictions, must be selected by a user. In order for the delay-locked loop to generate an output signal, the delay-locked loop must lock on the reference signal. However, if the reference signal is not within the range of input signals selected by the user, the delay-locked loop will not lock on reference signal and will not generate the desired output clock signal.
Finally, when aligning the phase of a generated clock to the phase of a reference clock, it is important that any changes to a delay select value of a digital delay line for adjusting the phase of a clock signal does not shift the phase of the generated signal beyond a maximum desirable shift. Because there is typically a recovery time for the delay-locked loop when a clock signal is compensated for delay, it is necessary to insure that the total phase shift introduced by a delay line used for phase alignment does not exceed a certain amount. Phase shifting in a delay lock loop that may exceed a maximum amount of shifting could result in loss of lock for the delay-locked loop.
Accordingly, there is a need for a method of and circuit for effectively deskewing clock signals in an integrated circuit.